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CMOS Layout Design Engineer or Sr Engineer

CMOS Layout Design Engineer or Sr Engineer

Lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits.
詳細介紹
Responsibilities:
  • Lead Top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits
  • Perform schematic-driven layout and design constraints
  • Design die-area efficient layouts according to circuit designer requirements
  • Perform block or top-level layout designs
  • Perform floor-planning, power line planning, shielding, and device-matching layout
  • Verify layouts. Pass DRC, LVS, and ERC
  • Contribute to various chip-level routing and layout needs
  • Support other projects as needed by management
Qualifications & Requirements:
  • AA/AS Degree in Layout Design or related field or equivalent experience
  • 3-8+ years’ experience with layout design for analog and full-custom digital blocks
  • Proficient in using layout editing tools in the Cadence Virtuoso design environment
  • Solid working knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
  • Conceptual understanding of layout topics such as parasitics, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
  • Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
  • Experience in chip‐level floor planning and analog block integration.